The present invention generally relates to a semiconductor integrated circuit device, and particularly to an improvement of a contact hole structure used for making an electrical contact between a silicon substrate and a conductive film such as an electrode and a wiring (interconnection) line. More particularly, the present invention relates to a semiconductor integrated circuit device having a contact hole structure which can provide a pitch between adjacent electrodes or wiring lines which is narrower than a minimum pitch obtained by photolithography technology.
Generally, an electrode or a wiring line of a semiconductor integrated circuit device is formed by forming a contact hole in an insulation film formed on the surface of a substrate and then forming an electrode or a wiring line which is provided so as to cover the contact hole and which is a little larger (wider) than the contact hole. The use of the larger electrode or wiring line is intended to cope with the occurrence of a positional error or alignment error which may occur at the time of forming an electrode or wiring line. That is, the electrode or wiring line is designed to have an alignment tolerance. The alignment tolerance functions to prevent a surface area of the substrate from appearing even when an alignment error occurs. If a surface area appears due to the alignment error, it is exposed to etching, and therefore a recess portion is formed in the substrate.
The distance between the centers of neighboring electrodes (hereinafter referred to as an electrode pitch) which are in contact with the substrate through respective contact holes, is necessarily defined as a function of various parameters such as the size of a contact hole, an alignment tolerance of an electrode, and a distance between opposed edges of the neighboring electrodes. Generally, the above parameters depend on the accuracy of photolithography technology. As a result, the electrode pitch depends on the accuracy of photolithography technology. This means that there is a limit on the electrode pitch which can be obtained by photolithography technology. The above holds true for a wiring line which is in contact with a substrate through a contact hole.
In order to enhance the integration density of a semiconductor integrated circuit device, it is essential to reduce the electrode pitch. However, with current production processes which employ photolithography technology, a further reduced electrode pitch cannot be obtained. For this reason, a means which enables the electrode pitch to be reduced, is desired.